`timescale 1ns/1ps
module sc1_tb (
    
);

reg a,b,c;
wire f;
sc1 sc1(
     .a(a)
    ,.b(b)
    ,.c(c)
    ,.f(f)
);

initial begin
   a = 1'b0;
   b = 1'b0;
   c = 1'b0;
   forever begin
     #1 a = ~a;
     #2 b = ~b;
     #4 c = ~c;
   end
 end
endmodule //sc1_tb